• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Integrated nonvolatile memory device comprising at least one integrated EEPROM type memory cell (CEL) comprising a floating gate transistor (TR) and a selection transistor (TA) connected in series between a source line (SL) and a bit line (BL) and programming means (MPR) of said at least one memory cell. The selection transistor (TA) is connected between the floating gate transistor (TR) and said source line (SL), and the programming means (MPR) is configured to program said at least one memory cell with a voltage of shared programming between a positive voltage (Vpp +) and a negative voltage (Vpp-).
    公开号:FR3029343A1
    申请号:FR1461549
    申请日:2014-11-27
    公开日:2016-06-03
    发明作者:Francois Tailliet
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    [0001] Electrically Erasable and Programmable Type Compact Memory Device Embodiments of the invention relate to memories, particularly electrically erasable and programmable non-volatile memories (EEPROMs).
    [0002] In the EEPROMs, the logical value of a bit stored in a memory point is represented by the value of the threshold voltage of a floating gate transistor, which can be modified at will by programming or programming operations. erasure. The programming or the erasure of a floating gate transistor consists in the injection or the extraction of the electric charges in the gate of the transistor by tunnel effect ("Fowler-Nordheim" effect) by means of a high voltage of Vpp writing which can be of the order of 10 to 20 volts, typically 13 volts. This high voltage of 13 volts, necessary for writing EEPROM memories is non-reducible and is very restrictive in terms of technology and product reliability. In fact, the lithographic reduction, that is to say the increase of the engraving fineness, leads to a decrease of the operating voltages, and this high writing voltage becomes more problematic in terms in particular of leakage of the source junctions. / drain of the transistors as well as in terms of breakdown of the gate oxides. Therefore, these risks of breakdown and premature aging of the transistors have a direct impact on the reliability of the product. A so-called "shared voltage" or "split voltage" solution according to an Anglo-Saxon denomination usually used by those skilled in the art, has been envisaged. More precisely, the high voltage Vpp necessary for the programming of the memory planes is shared between a positive voltage Vpp + and a negative voltage Vpp- so that the difference (Vpp + - Vpp-) is equal to Vpp. Thus, in such an approach, a voltage Vpp + of the order of 4 volts and a voltage Vpp- of the order of -9 volts will be chosen. Such a solution allows a relaxation of the stress on the voltage withstand of the transistors. However, it has the disadvantage of making more complicated the process of manufacturing the memory plan since it requires a so-called "triple box" technology because of the negative voltage of the order of a few volts. Furthermore, the design of the control is more complicated since it is necessary to provide negative voltage switching, which also has a negative impact on the surface of the memory plane. Indeed, a negative voltage switching is expensive in place in the memory plane (use of PMOS transistors) at the control transistors of the control gates of the floating gate transistors. According to one embodiment, there is provided a more compact EEPROM type memory device compatible with a "shared voltage" type architecture. According to one embodiment, there is provided such a memory device compatible with a bit granularity, a granularity byte (s) or a granularity page and which operates by effect "FowlerNordheim" both erase and programming. According to one aspect, there is provided a nonvolatile memory device, comprising at least one integrated EEPROM type memory cell comprising a floating gate transistor and a selection transistor (also called access transistor or isolation transistor) connected in series between a source line and a bit line, and programming means of said at least one memory cell.
    [0003] According to a general characteristic of this aspect, the selection transistor is connected between the floating gate transistor and said source line, and the programming means are configured to program said at least one memory cell with a programming voltage shared between a positive voltage and a negative voltage. The source-side placement of the selection transistor thus makes it possible to produce particularly dense structures, in particular when the selection transistor is a vertical MOS transistor whose gate region is for example made within a trench formed in a semiconductor box. Moreover, the selection transistor is advantageously not used to select the memory cell during programming. Indeed, when the memory device comprises a matrix memory plane, the selection during programming and in a selected column, between two memory cells of the same bit line, one belonging to an unselected row and the other belonging to an unselected row, is then done by the floating gate voltage (for example -9 volts for a selected row and +2 volts for an unselected row) and no longer by switching or not (depending on whether the row is selected or not) a voltage at the drain of the floating gate state transistor. According to one embodiment, the programming means are further configured to perform a programming of the memory cell comprising a blocking of the selection transistor. The blocking of each selection transistor during programming avoids the return of current to the source line.
    [0004] In deletion the selection transistor is on. The selection transistor remains in read mode and it is only during this operation that it is intended to play a selection role (that is to say that its gate voltage depends on the selected state of the row to which it belongs).
    [0005] Moreover, its source-side placement makes it possible to operate it under low voltage, which makes it easy to reduce its size or to modify its structure. When the selection transistor is a vertical MOS transistor, the active zone of the floating gate transistor and the active zone of the selection transistor are advantageously located in the same semiconductor well isolated from the remainder of the integrated circuit substrate by a buried semiconductor layer (for example). example that commonly referred to by those skilled in the art under the acronym "N-layer iso") also forming said source line and the source region of the selection transistor. This buried layer thus has a dual role of conveying the source potential to the selection transistor and isolating the semiconductor casing from the mass for the reading operation when the casing is brought to a negative reading potential (for example -1 volt ). According to one embodiment, the device comprises a matrix memory plane comprising columns of memory words formed respectively on each row of the memory array by groups of memory cells. It is then particularly advantageous that the device comprises separate source lines respectively associated with the different columns of memory words and intended to receive different voltages depending on the selection or not of the memory word column, during a cycle of data. erasure-programming of the memory device. Such an embodiment makes it possible in particular to be compatible with a grouping within control blocks, control elements, for example inverters, controlling the control gates of the floating gate transistors of the memory cells. Such a grouping is for example described in the French patent application No. 1461339 entitled "compact non-volatile memory device". Indeed, by grouping these control elements, the surface of the memory plane is reduced while decreasing the periodic failure of the uniformity of the memory plane which existed notably when these control elements were distributed every two columns of the memory plane by example. And, this periodic breaking of the uniformity of the memory plane generally causes variations in the behavior of the memory cells close to the control elements. In an architecture of the "shared voltage" type, it is particularly advantageous that all the NMOS transistors of the inverters of the control block are arranged in the same first semiconductor well and that all the PMOS transistors of the inverters of the control blocks are arranged in the same second semiconductor box. This allows additional space saving.
    [0006] However, such an arrangement combined with the grouping of control elements mentioned above, introduces specific electrical constraints that can be overcome by providing that the sources of the state transistors of the memory cells of the same column of memory words are connected to the same source line, the source lines of the different columns of memory words being distinct and intended to receive different voltages according to the selection or not of the memory word column, during a cycle. erase-programming of the memory device.
    [0007] In other words, it selectively powers the source lines to apply a specific source voltage for an unselected column and a selected row. Thus during an erase cycle, for a memory word located in a selected row and an unselected column and whose voltage on the control gates of its state transistors is floating in a wide range of voltages, it avoids the risk of parasitic erasure ("disturb") by the application of a voltage on the source line of this memory word. A particularly simple way of producing these distinct source lines consists, for example, in providing a buried layer comprising several mutually electrically isolated parts, each part extending under a column of memory words in the sense of the bit lines and forming the source line. associated with said memory word column. Each buried layer portion isolates from the rest of the substrate, the corresponding semiconductor box containing all the memory cells of said memory word column, all the semiconductor boxes being otherwise mutually electrically isolated.
    [0008] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments, in no way limiting, and the attached drawings in which: FIG. 1 schematically illustrates an example of an EEPROM memory device of FIG. prior art, and, - Figures 2 to 8 schematically illustrate different embodiments of a memory device according to the invention. FIG. 1 illustrates an example of a DIS memory device of the EEPROM type. The device comprises a memory plane PM comprising CEL memory cells connected to row selection lines delivering WLSW signals, and bit lines BL. The bit lines are grouped into COL columns, here comprising M bit lines BLo-BLm-i.
    [0009] M can be for example equal to 38, thus corresponding to useful 32-bit words (4 bytes) accompanied by 6 bits of error correction code (ECC). The memory cells connected to the same selection line form a word line and the memory cells CEL ,, k (k varying from 0 to M-1) of the same word line connected to the M bit lines of a column. COL, form a memory word MW, to store M bits. For the purpose of simplification, a single word MW ,, belonging to a column COL, and to a row i is represented in FIG.
    [0010] Each memory cell CEL ,, k comprises a floating gate state transistor TR ,, k and an access transistor (or selection or isolation transistor) TA ,, k of the MOS type. The transistor TA ,, k is controlled on its gate by the signal WLSW ,. Its drain is connected to the corresponding bit line BL and its source is connected to the drain of the floating gate transistor TR ,, k. A control element CGS, here a MOS transistor is also controlled on its gate by the signal WLSW, and delivers a control signal CG, on the control gates of all the floating gate transistors TR, k of the column COL, ( the word memory). The signal WLSW is delivered to the output terminal BS of a row decoder RDEC.
    [0011] The transistor CGS ,,, is also connected to a column selection line SCOL, connected to the output BS, of a column decoder CDEC, via a latch ("latch") of columns CGL, . Moreover, each bit line BLk of the column COL is connected to the line SCOL via a bit line lock CGBLk. Each bit line is also connected in a conventional manner to a sense amplifier via a column selection transistor, a read transistor and a multiplexing bus (these elements are not represented on Figure 1 for simplification purposes). The column selection transistors are driven by the column selection signal SCOL, while the read transistors are driven by a read signal. The read amplifiers connected at the input of the multiplex bus and at the output to another bus, make it possible to read the Mbits of a memory word. Finally, the sources of the floating gate transistors TR of the cells are connected to a source line SL. In a conventional memory array architecture, there is a column of control elements CGS ,, per COL column, i.e. in memory word. With respect to a prior art CEL memory cell, such as that illustrated in FIG. 1, a memory cell CEL according to one embodiment of the invention comprises, as illustrated in FIG. 2, the connected selection transistor TA. between the floating gate transistor TR and the source line SL. More precisely, in the example of FIG. 2, the source S of the selection transistor TA is connected to the source line SL while its drain D is connected to a first conduction electrode, for example the source S, of the transistor floating gate TR. The other conduction electrode, for example the drain D, of the floating gate transistor TR is connected to the bit line BL. The control gate GRC of the floating gate transistor TR receives the signal CG from a control element CGS which can be of any known type, for example an inverter. The control electrode of the control element CGS is controlled by the signal WLSW delivered by the row decoder. Furthermore, the gate GRA of the access transistor TA is controlled by a signal WLBL also emanating from the row decoder. In the embodiment of FIG. 2, the signals WLBL and WLSW are distinct. This makes it possible to reduce the risk of breakdown of the gate oxide of the access transistor. It is technically conceivable that these signals WLSW and WLBL are confused. This would simplify the architecture and the physical implementation but would induce higher voltages on the gate of the selection transistor TA or transistors of the control element CGS, possibly leading to an accelerated aging of these transistors, an unfavorable drift of their characteristics, even their breakdown. The memory device DIS also comprises programming means MPR, of known structure, configured to program the CEL cell with a programming voltage shared between a positive voltage Vpp + and a negative voltage VppPlus precisely, writing a data in the cell comprises an erasure of the cell followed by a programming of the cell. And to program a data value equal to "1" in an erased cell (containing a "0"), the voltage Vpp + (for example 4 volts) is applied to the bit line BL and the voltage Vpp- (for example -9 volts ) on the control gate GRC of the transistor TR (the voltage Vpp- is the signal CG), so as to obtain an adequate programming voltage (for example 13 volts). It is not necessary to use the selection transistor TA when programming the cell, because the selection of the cell is made by means of the floating gate voltage (-9 volts for the selected cell and 2 volts for the unselected cell).
    [0012] Also the programming means MPR are configured to block the transistor TA by delivering a zero WLBL voltage on the gate GRA of this transistor. However, the selection transistor TA remains in read mode where it plays its selection role and its source-side placement makes it possible to operate it under low voltage, which makes it possible to reduce its size or to modify its structure. Placing the selection transistor TA on the source side therefore makes it possible to densify the memory cell CEL. This densification is even greater when the selection transistor TA is a vertical transistor such as that illustrated schematically in FIGS. 3 and 4, FIG. 3 being the section along the line of FIG. 4. In these figures, the active zone of FIG. floating gate transistor TR and the active area of the selection transistor TA are located in the same semiconductor box CSP, here a conductivity box P, isolated from the rest of the substrate SB of the integrated circuit by a buried semiconductor layer 10 (commonly referred to as those skilled in the art under the name N-layer N) of conductivity type N, this layer 10 forming the source line SL and the source region S of the selection transistor TA. The CSP casing is also isolated laterally by an insulating region RIS for example of the shallow trench type (STI: Shallow Trench Isolation).
    [0013] The transistor TA also comprises a vertical semiconductor region GRA forming the gate region of this transistor and isolated from the CSP box and the buried layer by a gate oxide OX.
    [0014] In practice, this gate region is produced by etching a trench in the substrate SB, oxidation of the walls of the trench and filling with polysilicon for example. Alternatively the GRA region could be metallic. The cell CEL furthermore comprises a first semiconductor zone Z1, doped here N +, that is to say of the same type of conductivity as that of the source line 10, and forming at the same time the drain region of the selection transistor. TA and a first conduction electrode of the floating gate transistor TR. Another active zone portion Z3 is disposed on the other side of the GRA gate region. It results from the piercing of the active zone for the realization of the trench and it is electrically inactive for the cell. The caisson CSP furthermore comprises a second semiconductor region Z2, of the same conductivity type as that of the source line, in this case an N + doped region, forming a second conduction electrode of the floating gate transistor, this region Z2 being electrically coupled to the bit line BL by a CTC metal contact. Similarly, the gate region GRA is electrically coupled to the line of words carrying the signal WLBL by a contact not shown here for simplification purposes. While a single cell CEL has been shown in FIGS. 2 to 4, the memory device DIS generally comprises (FIG. 5) a matrix memory plane PM comprising columns COL, of memory words MW, respectively formed on each row RG, of the memory array by groups of memory cells CEL ,, k (k varying for example from 0 to M-1 for memory words of M bits). FIG. 6 represents three tables indicating the different values of the different signals in the operations of erasure, programming and reading of the memory plane in the case where each control element CGS ,, j is for example an inverter, distinguishing the cases where a column is selected or not selected in combination with the cases where a row is selected or not selected and for each possible logical value (0 or 1) of a data item to be programmed or read. In these tables, the BL column denotes by language abuse, the voltage on the bit line BL and the CSP column designates the polarization of the CSP box.
    [0015] With regard to the erase operation, Vwle designates the value of the WLBL signal in this operation to make the selection transistor passing. As an indication Vwle can be of the order of 1 volt to 5 volts and could be directly the supply voltage Vdd of the device.
    [0016] With regard to the read operation, Vwlr designates the value of the signal WLBL in this operation to make the selection transistor passing, CGread denotes the read voltage applied to the control gate of the floating gate transistor of a cell and Vhigh is the value of the voltage present on the bit line BL when reading a logic "0". FIG. 7, which is a view from above of a particular embodiment of the memory plane PM of a memory device DIS and FIG. 8 which is a section along the line VIII-VIII of FIG. 7, show an architecture in which separate source lines SLj are respectively associated with the different columns COUj of memory words of the memory plane and intended to receive different voltages according to the selection or not of the memory word column, during a cycle of erase-programming the memory device.
    [0017] In this regard, the buried layer 10 comprises a plurality of mutually electrically isolated portions 10j, each portion extending under a column of memory words COUj in the DBL direction of the bit lines. Each part 10j forms the source line associated with the column COLJ of memory words and isolates the corresponding semiconductor CSPJ box from the rest of the substrate SB. The CSPJ semiconductor box contains all the memory cells of the COLJ word-memory column. All the semiconductor casings (CSPJ) are moreover mutually electrically isolated, for example by N-doped wells 11. Such an architecture is as indicated above, compatible with a grouping of control elements CGS ,, j within blocks. control device in combination with a shared voltage architecture in which all the transistors N of the various control elements (inverters for example) grouped are located in the same first semiconductor box and in which the transistors P grouped inverters are also located in the same second semiconductor box. Such a shared voltage architecture and grouped control elements is for example described in the aforementioned French patent application No. 1461339. As can be seen in the tables of FIG. 6, the bit lines of a column selected during the programming of a logic "1" are at 4 volts while those of an unselected column are at 0. volt. However, it is possible that the proximity of such selected bit lines at 4 volts and not selected at 0 volts during programming creates leaks that can be significant. It is possible to reduce these leaks or even cancel them, if the programming means are further configured to apply a substrate effect during programming. This substrate effect can be obtained either by a negative pumping of the bias voltage of the CSP box (for example -1 volt) or by shifting the voltages between the selected bit lines and the unselected bit lines. Thus, for example, the bit line of a selected column will be increased to 5 volts when programming a logic "1" instead of 4 volts while the bit line of a non-column
    权利要求:
    Claims (11)
    [0001]
    REVENDICATIONS1. Integrated nonvolatile memory device comprising at least one integrated EEPROM type memory cell (CEL) comprising a floating gate transistor (TR) and a selection transistor (TA) connected in series between a source line (SL) and a bit line (BL) and programming means (MPR) of said at least one memory cell, characterized in that the selection transistor (TA) is connected between the floating gate transistor (TR) and said line of source (SL), and the programming means (MPR) are configured to program said at least one memory cell with a programming voltage shared between a positive voltage (Vpp +) and a negative voltage (Vpp-)
    [0002]
    2. Device according to claim 1, wherein the selection transistor (TA) is a vertical MOS transistor.
    [0003]
    3. Device according to claim 2, wherein the active area of the floating gate transistor and the active area of the selection transistor are located in the same semiconductor box (CSP) isolated from the rest of the integrated circuit substrate by a buried semiconductor layer ( 10) also forming said source line and the source region of the selection transistor.
    [0004]
    4. Device according to claim 3, wherein said semiconductor box (CSP) comprises a vertical region (GRA) forming the gate region of the selection transistor (TA).
    [0005]
    5. Device according to claim 3 or 4, wherein the semiconductor box (CSP) comprises a first semiconductor region (Z1) of the same conductivity type as that of the source line (SL) and forming both the drain region of the selection transistor (TA) and a first conduction electrode of the floating gate transistor (TR), and a second semiconductor region (Z2) of the same conductivity type as that of the source line (SL) forming a second electrode of the floating gate transistor electrically coupled to said bit line.
    [0006]
    6. Device according to one of the preceding claims, wherein the programming means (MPR) are further configured to perform a programming of the memory cell comprising a blocking of the selection transistor (TA).
    [0007]
    7. Device according to one of the preceding claims, wherein the selection transistor is intended to play a selection role only during a read operation of the memory cell.
    [0008]
    8. Device according to one of the preceding claims comprising a matrix memory plane (PM) comprising columns (COL) of memory words (MW,) respectively formed on each row of the memory array by groups of memory cells (CEL).
    [0009]
    9. Device according to claim 8, comprising separate source lines (SLj) respectively associated with the different columns (COL) of memory words and intended to receive different voltages depending on the selection or not of the word memory column. during an erase-programming cycle of the memory device.
    [0010]
    The device according to claims 3 and 9, wherein said buried layer comprises a plurality of mutually electrically isolated portions (10j), each portion extending under a column (COL) of memory words in the sense of the bit lines and forming the source line associated with said memory word column, each part (10j) of insulating buried layer of the rest of the substrate (SB) the corresponding semiconductor box (CS13j) containing all the memory cells of said memory word column, all the semiconductor casings (CS13j) being mutually electrically isolated.
    [0011]
    11. Device according to one of the preceding claims, wherein the programming means (MPR) are further configured to apply a substrate effect during programming.
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    引用文献:
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    FR3071355B1|2017-09-20|2019-08-30|StmicroelectronicsSas|MEMORY CELL-COMPACT EEPROM|
    FR3074605B1|2017-12-05|2020-01-17|StmicroelectronicsSas|METHOD FOR DETECTING A POSSIBLE THINNING OF A SUBSTRATE OF A CIRCUIT INTEGRATED BY ITS REAR PANEL, AND ASSOCIATED DEVICE|
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    法律状态:
    2015-10-23| PLFP| Fee payment|Year of fee payment: 2 |
    2016-06-03| PLSC| Publication of the preliminary search report|Effective date: 20160603 |
    2016-10-24| PLFP| Fee payment|Year of fee payment: 3 |
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    2021-08-06| ST| Notification of lapse|Effective date: 20210705 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1461549|2014-11-27|
    FR1461549A|FR3029343B1|2014-11-27|2014-11-27|COMPACT MEMORY DEVICE OF ELECTRICALLY ERASABLE AND PROGRAMMABLE TYPE|FR1461549A| FR3029343B1|2014-11-27|2014-11-27|COMPACT MEMORY DEVICE OF ELECTRICALLY ERASABLE AND PROGRAMMABLE TYPE|
    US14/864,354| US9583193B2|2014-11-27|2015-09-24|Compact memory device of the EEPROM type with a vertical select transistor|
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